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p89c51ra2xx/rb2xx/rc2xx/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram preliminary data supersedes data of 2002 may 20 2002 jul 18 integrated circuits
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2 2002 jul 18 description the p89c51ra2/rb2/rc2/rd2xx contains a non-volatile 8kb/16kb/32kb/64kb flash program memory that is both parallel programmable and serial in-system and in-application programmable. in-system programming (isp) allows the user to download new code while the microcontroller sits in the application. in-application programming (iap) means that the microcontroller fetches new program code and reprograms itself while in the system. this allows for remote programming over a modem link. a default serial loader (boot loader) program in rom allows serial in-system programming of the flash memory via the uart without the need for a loader in the flash code. for in-application programming, the user program erases and reprograms the flash memory by use of standard routines contained in rom. the device supports 6-clock/12-clock mode selection by programming a flash bit using parallel programming or in-system programming. in addition, an sfr bit (x2) in the clock control register (ckcon) also selects between 6-clock/12-clock mode. additionally, when in 6-clock mode, peripherals may use either 6 clocks per machine cycle or 12 clocks per machine cycle. this choice is available individually for each peripheral and is selected by bits in the ckcon register. this device is a single-chip 8-bit microcontroller manufactured in an advanced cmos process and is a derivative of the 80c51 microcontroller family. the instruction set is 100% compatible with the 80c51 instruction set. the device also has four 8-bit i/o ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced uart and on-chip oscillator and timing circuits. the added features of the p89c51ra2/rb2/rc2/rd2xx make it a powerful microcontroller for applications that require pulse width modulation, high-speed i/o and up/down counting capabilities such as motor control. features ? 80c51 central processing unit ? on-chip flash program memory with in-system programming (isp) and in-application programming (iap) capability ? boot rom contains low level flash programming routines for downloading via the uart ? can be programmed by the end-user application (iap) ? parallel programming with 87c51 compatible hardware interface to programmer ? supports 6-clock/12-clock mode via parallel programmer (default clock mode after chiperase is 12-clock) ? 6-clock/12-clock mode flash bit erasable and programmable via isp ? 6-clock/12-clock mode programmable aon-the-flyo by sfr bit ? peripherals (pca, timers, uart) may use either 6-clock or 12-clock mode while the cpu is in 6-clock mode ? speed up to 20 mhz with 6-clock cycles per machine cycle (40 mhz equivalent performance); up to 33 mhz with 12 clocks per machine cycle ? fully static operation ? ram expandable externally to 64 kbytes ? four interrupt priority levels ? seven interrupt sources ? four 8-bit i/o ports ? full-duplex enhanced uart framing error detection automatic address recognition ? power control modes clock can be stopped and resumed idle mode power down mode ? programmable clock-out pin ? second dptr register ? asynchronous port reset ? low emi (inhibit ale) ? programmable counter array (pca) pwm capture/compare
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 3 selection table type memory timers serial interfaces ram rom otp flash # of timers pwm pca wd uart i 2 c can spi adc bits/ch. i/o pins interrupts (ext.)/levels program security default clock rate 1 optional clock rate 1 reset active low/high? max. freq. at 6-clk / 12-clk (mhz) freq. range at 3v (mhz) freq. range at 5v (mhz) p89c51rd2xx 1k 64k 4 32 7(2)/4 12-clk 6-clk h 20/33 0-20/33 p89c51rc2xx 512b 32k 4 32 7(2)/4 12-clk 6-clk h 20/33 0-20/33 P89C51RB2xx 512b 16k 4 32 7(2)/4 12-clk 6-clk h 20/33 0-20/33 p89c51ra2xx 512b 8k 4 32 7(2)/4 12-clk 6-clk h 20/33 0-20/33 note: 1. p89c51rx2hxx devices have a 6-clk default clock rate (12-clk optional). please also see device comparison table. device comparison table item 1st generation of rx2 devices 2nd generation of rx2 devices (this data sheet) difference type description p89c51rx2 h xx(x) p89c51rx2xx(x) no more letter `h' programming algo- rithm when using a parallel programmer, be sure to select p89c51rx2 h xx(x) devices when using a parallel programmer, be sure to select p89c51rx2xx(x) de- vices (no more letter `h') different programming algorithm due to process change clock mode (i) 6-clk default, otp configuration bit to program to 12-clk mode using parallel programmer ( cannot be programmed back to 6-clk) 12-clk default, flash configuration bit to program to 6-clk mode using paral- lel programmer or isp ( can be repro- grammed) more flexibility for the end user, more compatibility to older p89c51rx+ parts clock mode (ii) n/a 6-clock/12-clock mode programmable aon the flyo by sfr bit x2 (ckcon.0) clock mode can be changed by software peripheral clock modes n/a peripherals can be run in 12-clk mode while cpu runs in 6-clk mode more flexibility, lower power con- sumption flash block structure two 8-kbyte blocks 13 16-kbyte blocks 216 4-kbyte blocks more flexibility ordering information part order memory temperature voltage frequency (mhz) part order number 1 flash ram range ( c) and package voltage range 6-clock mode 12-clock mode dwg # 1. p89c51ra2ba/01 8 kb 512 b 0 to +70, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 2. p89c51ra2bbd/01 8 kb 512 b 0 to +70, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1 3. P89C51RB2ba/01 16 kb 512 b 0 to +70, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 4. P89C51RB2bbd/01 16 kb 512 b 0 to +70, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1 5. p89c51rc2bn/01 32 kb 512 b 0 to +70, pdip 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot129-1 6. p89c51rc2ba/01 32 kb 512 b 0 to +70, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 7. p89c51rc2fa/01 32 kb 512 b 40 to +85, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 8. p89c51rc2bbd/01 32 kb 512 b 0 to +70, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1 9. p89c51rc2fbd/01 32 kb 512 b 40 to +85, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1 10. p89c51rd2bn/01 64 kb 1024 b 0 to +70, pdip 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot129-1 11. p89c51rd2ba/01 64 kb 1024 b 0 to +70, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 12. p89c51rd2bbd/01 64 kb 1024 b 0 to +70, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1 13. p89c51rd2fa/01 64 kb 1024 b 40 to +85, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 note: 1. the part marking will not include the a/01o.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 4 block diagram 1 su01606 accelerated 80c51 cpu (12-clk mode, 6-clk mode) 8k / 16k / 32k / 64 kbyte code flash 512 / 1024 byte data ram port 3 configurable i/os port 2 configurable i/os port 1 configurable i/os port 0 configurable i/os oscillator crystal or resonator full-duplex enhanced uart timer 0 timer 1 timer 2 programmable counter array (pca) watchdog timer
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 5 block diagram cpu oriented su01065 psen ea v pp ale rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch flash register b acc stack pointer tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr's multiple p1.0p1.7 p3.0p3.7 p0.0p0.7 p2.0p2.7 sfrs timers p.c.a. 8 8 16
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 6 logic symbol port 0 port 1 port 2 port 3 address and data bus address bus t2 t2ex rxd txd int0 int1 t0 t1 wr rd secondary functions rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 su01302 pinning plastic dual in-line package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 t2/p1.0 t2ex/p1.1 eci/p1.2 cex0/p1.3 cex1/p1.4 cex2/p1.5 cex3/p1.6 rst rxd/p3.0 txd/p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 cex4/p1.7 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p2.5/a13 p2.6/a14 p2.7/a15 psen ale/prog ea /v pp p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v cc dual in-line package su00021 plastic leaded chip carrier lcc 6140 7 17 39 29 18 28 pin function 1 nic* 2 p1.0/t2 3 p1.1/t2ex 4 p1.2/eci 5 p1.3/cex0 6 p1.4/cex1 7 p1.5/cex2 8 p1.6/cex3 9 p1.7/cex4 10 rst 11 p3.0/rxd 12 nic* 13 p3.1/txd 14 p3.2/int0 15 p3.3/int1 pin function 16 p3.4/t0 17 p3.5/t1 18 p3.6/wr 19 p3.7/rd 20 xtal2 21 xtal1 22 v ss 23 nic* 24 p2.0/a8 25 p2.1/a9 26 p2.2/a10 27 p2.3/a11 28 p2.4/a12 29 p2.5/a13 30 p2.6/a14 pin function 31 p2.7/a15 32 psen 33 ale/prog 34 nic* 35 ea /v pp 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc su00023 * no internal connection plastic quad flat pack lqfp 44 34 1 11 33 23 12 22 pin function 1 p1.5/cex2 2 p1.6/cex3 3 p1.7/cex4 4 rst 5 p3.0/rxd 6 nic* 7 p3.1/txd 8 p3.2/int0 9 p3.3/int1 10 p3.4/t0 11 p3.5/t1 12 p3.6/wr 13 p3.7/rd 14 xtal2 15 xtal1 pin function 16 v ss 17 nic* 18 p2.0/a8 19 p2.1/a9 20 p2.2/a10 21 p2.3/a11 22 p2.4/a12 23 p2.5/a13 24 p2.6/a14 25 p2.7/a15 26 psen 27 ale/prog 28 nic* 29 ea /v pp 30 p0.7/ad7 pin function 31 p0.6/ad6 32 p0.5/ad5 33 p0.4/ad4 34 p0.3/ad3 35 p0.2/ad2 36 p0.1/ad1 37 p0.0/ad0 38 v cc 39 nic* 40 p1.0/t2 41 p1.1/t2ex 42 p1.2/eci 43 p1.3/cex0 44 p1.4/cex1 su01400 * no internal connection
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 7 pin descriptions mnemonic pin number type name and function mnemonic pdip plcc lqfp type name and function v ss 20 22 16 i ground: 0 v reference. v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.00.7 3932 4336 3730 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. p1.0p1.7 18 29 4044, 13 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups on all pins. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). alternate functions for p89c51ra2/rb2/rc2/rd2xx port 1 include: 1 2 40 i/o t2 (p1.0): timer/counter 2 external count input/clockout (see programmable clock-out) 2 3 41 i t2ex (p1.1): timer/counter 2 reload/capture/direction control 3 4 42 i eci (p1.2): external clock input to the pca 4 5 43 i/o cex0 (p1.3): capture/compare external i/o for pca module 0 5 6 44 i/o cex1 (p1.4): capture/compare external i/o for pca module 1 6 7 1 i/o cex2 (p1.5): capture/compare external i/o for pca module 2 7 8 2 i/o cex3 (p1.6): capture/compare external i/o for pca module 3 8 9 3 i/o cex4 (p1.7): capture/compare external i/o for pca module 4 p2.0p2.7 2128 2431 1825 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when em itting 1s. during accesses to external data memory that use 8-bit addresses (mov @ri), port 2 emits the contents of the p2 special function register. p3.0p3.7 1017 11, 1319 5, 713 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the p89c51ra2/rb2/rc2/rd2xx, as listed below: 10 11 5 i rxd (p3.0): serial input port 11 13 7 o txd (p3.1): serial output port 12 14 8 i int0 (p3.2): external interrupt 13 15 9 i int1 (p3.3): external interrupt 14 16 10 i t0 (p3.4): timer 0 external input 15 17 11 i t1 (p3.5): timer 1 external input 16 18 12 o wr (p3.6): external data memory write strobe 17 19 13 o rd (p3.7): external data memory read strobe rst 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal resistor to v ss permits a power-on reset using only an external capacitor to v cc . ale 30 33 27 o address latch enable: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted twice every machine cycle, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ale can be disabled by setting sfr auxiliary.0. with this bit set, ale will be active only during a movx instruction.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 8 mnemonic name and function type pin number mnemonic name and function type lqfp plcc pdip psen 29 32 26 o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea /v pp 31 35 29 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations. if ea is held high, the device executes from internal program memory. the value on the ea pin is latched when rst is released and any subsequent changes have no effect. this pin also receives the programming supply voltage (v pp ) during flash programming. xtal1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator amplifier. note: to avoid alatch-upo effect at power-on, the voltage on any pin (other than v pp ) must not be higher than v cc + 0.5 v or less than v ss 0.5 v.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 9 table 1. special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h auxr# auxiliary 8eh extram ao xxxxxx00b auxr1# auxiliary 1 a2h enboot gf2 0 dps xxxxxxx0b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ccap0h# module 0 capture high fah xxxxxxxxb ccap1h# module 1 capture high fbh xxxxxxxxb ccap2h# module 2 capture high fch xxxxxxxxb ccap3h# module 3 capture high fdh xxxxxxxxb ccap4h# module 4 capture high feh xxxxxxxxb ccap0l# module 0 capture low eah xxxxxxxxb ccap1l# module 1 capture low ebh xxxxxxxxb ccap2l# module 2 capture low ech xxxxxxxxb ccap3l# module 3 capture low edh xxxxxxxxb ccap4l# module 4 capture low eeh xxxxxxxxb ccapm0# module 0 mode dah ecom capp capn mat tog pwm eccf x0000000b ccapm1# module 1 mode dbh ecom capp capn mat tog pwm eccf x0000000b ccapm2# module 2 mode dch ecom capp capn mat tog pwm eccf x0000000b ccapm3# module 3 mode ddh ecom capp capn mat tog pwm eccf x0000000b ccapm4# module 4 mode deh ecom capp capn mat tog pwm eccf x0000000b df de dd dc db da d9 d8 ccon*# pca counter control d8h cf cr ccf4 ccf3 ccf2 ccf1 ccf0 00x00000b ch# pca counter high f9h 00h ckcon# clock control 8fh wdx2 pcax2 six2 t2x2 t1x2 t0x2 x2 x0000000b cl# pca counter low e9h 00h cmod# pca counter mode d9h cidl wdte cps1 cps0 ecf 00xxx000b dptr: data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ie* interrupt enable 0 a8h ea ec et2 es et1 ex1 et0 ex0 00h bf be bd bc bb ba b9 b8 ip* interrupt priority b8h ppc pt2 ps pt1 px1 pt0 px0 x0000000b iph# interrupt priority high b7h ppch pt2h psh pt1h px1h pt0h px0h x0000000b 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1* port 1 90h cex4 cex3 cex2 cex1 cex0 eci t2ex t2 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh pcon# 1 power control 87h smod1 smod0 pof gf1 gf0 pd idl 00xxx000b * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits. 1. reset value depends on reset source.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 10 table 1. special function registers (continued) symbol description direct address bit address, symbol, or alternative port function msb lsb reset value d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00000000b rcap2h # timer 2 capture high cbh 00h rcap2l # timer 2 capture low cah 00h saddr# slave address a9h 00h saden# slave address mask b9h 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon* serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t 2 cp/rl 2 00h t2mod# timer 2 mode control c9h t2oe dcen xxxxxx00b th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h th2# timer high 2 cdh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tl2# timer low 2 cch 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h wdtrst watchdog timer reset a6h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits. oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. minimum and maximum high and low times specified in the data sheet must be observed. this device is configured at the factory to operate using 12 clock periods per machine cycle, referred to in this datasheet as a12-clock modeo. it may be optionally configured on commercially available flash programming equipment or via isp or via software to operate at 6 clocks per machine cycle, referred to in this datasheet as a6-clock modeo. (this yields performance equivalent to twice that of standard 80c51 family devices). also see next page.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 11 clock control register (ckcon) this device provides control of the 6-clock/12-clock mode by means of both an sfr bit (x2) and a flash bit (fx2, located in the security block). the flash clock control bit, fx2, when programmed (6-clock mode) supercedes the x2 bit (ckcon.0). the ckcon register also provides individual control of the clock rates for the peripherals devices. when running in 6-clock mode each peripheral may be individually clocked from either fosc/6 or fosc/12. when in 12-clock mode, all peripheral devices will use fosc/12. the ckcon register is shown below. x2 bit symbol function ckcon.7 reserved. ckcon.6 wdx2 watchdog clock; 0 = 6 clocks for each wdt clock, 1 = 12 clocks for each wdt clock ckcon.5 pcax2 pca clock; 0 = 6 clocks for each pca clock, 1 = 12 clocks for each pca clock ckcon.4 six2 uart clock; 0 = 6 clocks for each uart clock, 1 = 12 clocks for each uart clock ckcon.3 t2x2 timer2 clock; 0 = 6 clocks for each timer2 clock, 1 = 12 clocks for each timer2 clock ckcon.2 t1x2 timer1 clock; 0 = 6 clocks for each timer1 clock, 1 = 12 clocks for each timer1 clock ckcon.1 t0x2 timer0 clock; 0 = 6 clocks for each timer0 clock, 1 = 12 clocks for each timer0 clock ckcon.0 x2 cpu clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle su01607 t0x2 t1x2 t2x2 six2 pcax2 wdx2 not bit addressable ckcon address = 8fh reset value = x0000000b 76543210 bits 1 through 6 only apply if 6 clocks per machine cycle is chosen (i.e. bit 0 = 1). if bit 0 = 0 (12 clocks per machine cycle) then all peripherals will have 12 clocks per machine cycle as their clock source. also please note that the clock divider applies to the serial port for modes 0 & 2 (fixed baud rate modes). this is because modes 1 & 3 (variable baud rate modes) use either timer 1 or timer 2. below is the truth table for the peripheral input clock sources. fx2 clock mode bit x2 peripheral clock mode bit (e.g., t0x2) cpu mode peripheral clock rate erased 0 x 12-clock (default) 12-clock (default) erased 1 0 6-clock 6-clock erased 1 1 6-clock 12-clock programmed x 0 6-clock 6-clock programmed x 1 6-clock 12-clock reset a reset is accomplished by holding the rst pin high for at least two machine cycles (12 oscillator periods in 6-clock mode, or 24 oscillator periods in 12-clock mode), while the oscillator is running. to ensure a good power-on reset, the rst pin must be high long e nough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-on, the voltage on v cc and rst must come up at the same time for a proper start-up. ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above v ih1 (min.) is applied to rst. the value on the ea pin is latched when rst is deasserted and has no further effect.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 12 low power modes stop clock mode the static design enables the clock speed to be reduced down to 0 mhz (stopped). when the oscillator is stopped, the ram and special function registers retain their values. this mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. for lowest power consumption the power down mode is suggested. idle mode in the idle mode (see table 2), the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode to save even more power, a power down mode (see table 2) can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their values down to 2 v and care must be taken to return v cc to the minimum specified operating voltages before the power down mode is terminated. either a hardware reset or external interrupt can be used to exit from power down. reset redefines all the sfrs but does not change the on-chip ram. an external interrupt allows both the sfrs and the on-chip ram to retain their values. to properly terminate power down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). with an external interrupt, int0 and int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power down. power-on flag the power-on flag (pof) is set by on-chip circuitry when the v cc level on the p89c51ra2/rb2/rc2/rd2xx rises from 0 to 5 v. the pof bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. the v cc level must remain above 3 v for the pof to remain unaffected by the v cc level. design consideration when the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. once ? mode the once (aon-circuit emulationo) mode facilitates testing and debugging of systems without the device having to be removed from the circuit. the once mode is invoked by: 1. pull ale low while the device is in reset and psen is high; 2. hold ale low as rst is deactivated. while the device is in once mode, the port 0 pins go into a float state, and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains active. while the device is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. programmable clock-out a 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50% duty cycle clock ranging from 61 hz to 4 mhz at a 16 mhz operating frequency in 12-clock mode (122 hz to 8 mhz in 6-clock mode). to configure the timer/counter 2 as a clock generator, bit c/t 2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation: oscillator frequency n (65536 rcap2h, rcap2l) n = 2 in 6-clock mode 4 in 12-clock mode where (rcap2h,rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode timer 2 roll-overs will not generate an interrupt. this is similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate generator and a clock generator simultaneously. note, however, that the baud-rate and the clock-out frequency will be the same. table 2. external pin status during idle and power-down mode mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 13 timer 0 and timer 1 operation timer 0 and timer 1 the atimero or acountero function is selected by control bits c/t in the special function register tmod. these two timer/counters have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 2 shows the mode 0 operation. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfn. the counted input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. (setting gate = 1 allows the timer to be controlled by external input intn , to facilitate pulse width measurements). trn is a control bit in the special function register tcon (figure 3). the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run flag (trn) does not clear the registers. mode 0 operation is the same for timer 0 as for timer 1. there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). mode 1 mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. mode 2 mode 2 configures the timer register as an 8-bit counter (tln) with automatic reload, as shown in figure 4. overflow from tln not only sets tfn, but also reloads tln with the contents of thn, which is preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer 0 as for timer 1. mode 3 timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 5. tl0 uses the timer 0 control bits: c/t , gate, tr0, and tf0 as well as pin int0 . th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the atimer 1o interrupt. mode 3 is provided for applications requiring an extra 8-bit timer on the counter. with timer 0 in mode 3, an 80c51 can look like it has three timer/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. gate c/t m1 m0 gate c/t m1 m0 bit symbol function tmod.3/ gate gating control when set. timer/counter ano is enabled only while aintn o pin is high and tmod.7 atrno control pin is set. when cleared timer ano is enabled whenever atrno control bit is set. tmod.2/ c/t timer or counter selector cleared for timer operation (input from internal system clock.) tmod.6 set for counter operation (input from atno input pin). m1 m0 operating 0 0 8048 timer: atlno serves as 5-bit prescaler. 0 1 16-bit timer/counter: athno and atlno are cascaded; there is no prescaler. 1 0 8-bit auto-reload timer/counter: athno holds a value which is to be reloaded into atlno each time it overflows. 1 1 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 (timer 1) timer/counter 1 stopped. su01580 timer 1 timer 0 not bit addressable tmod address = 89h reset value = 00h 76543 2 1 0 figure 1. timer/counter 0/1 mode control (tmod) register
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 14 intn pin timer n gate bit trn tln (5 bits) thn (8 bits) tfn interrupt control c/t = 0 c/t = 1 su01618 osc d* tn pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. figure 2. timer/counter 0/1 mode 0: 13-bit timer/counter it0 bit symbol function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. tcon.3 ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. tcon.1 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. su01516 ie0 it1 ie1 tr0 tf0 tr1 tf1 bit addressable tcon address = 88h reset value = 00h 76543210 figure 3. timer/counter 0/1 control (tcon) register
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 15 tln (8 bits) tfn interrupt control c/t = 0 c/t = 1 thn (8 bits) reload intn pin timer n gate bit trn su01619 osc d* tn pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. figure 4. timer/counter 0/1 mode 2: 8-bit auto-reload tl0 (8 bits) tf0 interrupt control th0 (8 bits) tf1 interrupt control tr1 int0 pin timer 0 gate bit tr0 su01620 c/t = 0 c/t = 1 *d = 6 in 6-clock mode; d = 12 in 12-clock mode. osc d* osc d* t0 pin figure 5. timer/counter 0 mode 3: two 8-bit counters
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 16 timer 2 operation timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/t 2 in the special function register t2con (see figure 6). timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator, which are selected by bits in the t2con as shown in table 3. capture mode in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2=0, then timer 2 is a 16-bit timer or counter (as selected by c/t 2 in t2con) which, upon overflowing sets bit tf2, the timer 2 overflow bit. this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register). if exen2= 1, timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt (which vectors to the same location as timer 2 overflow interrupt. the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt). the capture mode is illustrated in figure 7 (there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2ex pin transitions or osc/6 pulses (osc/12 in 12-clock mode).). auto-reload mode (up or down counter) in the 16-bit auto-reload mode, timer 2 can be configured (as either a timer or counter [c/t 2 in t2con]) then programmed to count up or down. the counting direction is determined by bit dcen (down counter enable) which is located in the t2mod register (see figure 8). when reset is applied the dcen=0 which means timer 2 will default to counting up. if dcen bit is set, timer 2 can count up or down depending on the value of the t2ex pin. figure 9 shows timer 2 which will count up automatically since dcen=0. in this mode there are two options selected by bit exen2 in t2con register. if exen2=0, then timer 2 counts up to 0ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by software means. if exen2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 are 1. in figure 10 dcen=1 which enables timer 2 to count up or down. this mode allows pin t2ex to control the direction of count. when a logic 1 is applied at pin t2ex timer 2 will count up. timer 2 will overflow at 0ffffh and set the tf2 flag, which can then generate an interrupt, if the interrupt is enabled. this timer overflow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. when a logic 0 is applied at pin t2ex this causes timer 2 to count down. the timer will underflow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. timer 2 underflow sets the tf2 flag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. the exf2 flag does not generate an interrupt in this mode of operation. (msb) (lsb) symbol position name and significance tf2 t2con.7 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk t2con.5 receive clock flag. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control for timer 2. a logic 1 starts the timer. c/t 2 t2con.1 timer or counter select. (timer 2) 0 = internal timer (osc/6 in 6-clock mode or osc/12 in 12-clock mode) 1 = external event counter (falling edge triggered). cp/rl 2 t2con.0 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. tf2 exf2 rclk tclk exen2 tr2 c/t 2 cp/rl 2 su01251 figure 6. timer/counter 2 (t2con) control register
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 17 table 3. timer 2 operating modes rclk + tclk cp/rl 2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 (off) osc n* c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin capture su01252 * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 7. timer 2 in capture mode not bit addressable symbol function e not implemented, reserved for future use.* t2oe timer 2 output enable bit. dcen down count enable bit. when set, this allows timer 2 to be configured as an up/down counter. e e e e e e t2oe dcen su00729 76543210 * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reser ved bit is indeterminate. bit t2mod address = 0c9h reset value = xxxx xx00b figure 8. timer 2 mode (t2mod) control register
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 18 osc n* c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload su01253 * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 9. timer 2 in auto-reload mode (dcen = 0) n* c/t 2 = 0 c/t 2 = 1 tl2 th2 tr2 control t2 pin su01254 ffh ffh rcap2l rcap2h (up counting reload value) t2ex pin tf2 interrupt count direction 1 = up 0 = down exf2 overflow (down counting reload value) toggle osc * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 10. timer 2 auto reload mode (dcen = 1)
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 19 c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) 16 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector reload 2 a0o a1o rx clock 16 tx clock a0o a1o a0o a1o timer 1 overflow note availability of additional external interrupt. smod rclk tclk su01629 n = 1 in 6-clock mode n = 2 in 12-clock mode osc n t2 pin figure 11. timer 2 in baud rate generator mode table 4. timer 2 generated commonly used baud rates baud rate timer 2 12-clock mode 6-clock mode osc freq rcap2h rcap2l 375 k 750 k 12 mhz ff ff 9.6 k 19.2 k 12 mhz ff d9 4.8 k 9.6 k 12 mhz ff b2 2.4 k 4.8 k 12 mhz ff 64 1.2 k 2.4 k 12 mhz fe c8 300 600 12 mhz fb 1e 110 220 12 mhz f2 af 300 600 6 mhz fd 8f 110 220 6 mhz f9 57 baud rate generator mode bits tclk and/or rclk in t2con (table 4) allow the serial port transmit and receive baud rates to be derived from either timer 1 or timer 2. when tclk= 0, timer 1 is used as the serial port transmit baud rate generator. when tclk= 1, timer 2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates one generated by timer 1, the other by timer 2. figure 11 shows the timer 2 in baud rate generation mode. the baud rate generation mode is like the auto-reload mode,in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2's overflow rate given below: modes 1 and 3 baud rates timer 2 overflow rate 16 the timer can be configured for either atimero or acountero operation. in many applications, it is configured for atimero operation (c/t 2=0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer it would increment every machine cycle (i.e., 1 / 6 the oscillator frequency in 6-clock mode, 1 / 12 the oscillator frequency in 12-clock mode). as a baud rate generator, it increments at the oscillator frequency in 6-clock mode ( osc / 2 in 12-clock mode). thus the baud rate formula is as follows: oscillator frequency [n* [65536 (rcap2h, rcap2l)]] modes 1 and 3 baud rates = * n = 16 in 6-clock mode 32 in 12-clock mode where: (rcap2h, rcap2l)= the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. the timer 2 as a baud rate generator mode shown in figure 11, is valid only if rclk and/or tclk = 1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable flag) is set, a 1-to-0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 20 when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. as a baud rate generator, timer 2 is incremented every state time (osc/2) or asynchronously from pin t2; under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. table 4 shows commonly used baud rates and how they can be obtained from timer 2. summary of baud rate equations timer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2 (p1.0) the baud rate is: baud rate timer 2 overflow rate 16 if timer 2 is being clocked internally, the baud rate is: baud rate f osc [n* [65536 (rcap2h, rcap2l)]] * n = 16 in 6-clock mode 32 in 12-clock mode where f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as: rcap2h, rcap2l 65536 f osc n* baud rate timer/counter 2 set-up except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. therefore, bit tr2 must be set, separately, to turn the timer on. see table 5 for set-up of timer 2 as a timer. also see table 6 for set-up of timer 2 as a counter. table 5. timer 2 as a timer t2con mode internal control (note 1) external control (note 2) 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h table 6. timer 2 as a counter tmod mode internal control (note 1) external control (note 2) 16-bit 02h 0ah auto-reload 03h 0bh notes: 1. capture/reload occurs only on timer/counter overflow. 2. capture/reload occurs on timer/counter overflow and a 1-to-0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generator mode.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 21 full-duplex enhanced uart standard uart operation the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency in 12-clock mode or 1/6 the oscillator frequency in 6-clock mode. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in 12-clock mode or 1/16 or 1/32 the oscillator frequency in 6-clock mode. mode 3: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren't being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. serial port control register the serial port control and status register is the special function register scon, shown in figure 12. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). baud rates the baud rate in mode 0 is fixed: mode 0 baud rate = oscillator frequency / 12 (12-clock mode) or / 6 (6-clock mode). the baud rate in mode 2 depends on the value of bit smod in special function register pcon. if smod = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. if smod = 1, the baud rate is 1/32 the oscillator frequency. in 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. mode 2 baud rate = 2 smod n (oscillator frequency) where: n = 64 in 12-clock mode, 32 in 6-clock mode the baud rates in modes 1 and 3 are determined by the timer 1 or timer 2 overflow rate. using timer 1 to generate baud rates when timer 1 is used as the baud rate generator (t2con.rclk = 0, t2con.tclk = 0), the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: mode 1, 3 baud rate = 2 smod n (timer 1 overflow rate) where: n = 32 in 12-clock mode, 16 in 6-clock mode the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either atimero or acountero operation, and in any of its 3 running modes. in the most typical applications, it is configured for atimero operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1, 3 baud rate = 2 smod n oscillator frequency 12 [256(th1)] where: n = 32 in 12-clock mode, 16 in 6-clock mode one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. figure 13 lists various commonly used baud rates and how they can be obtained from timer 1.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 22 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then rl will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if a valid stop bit was no t received. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the o ther modes, in any serial transmission. must be cleared by software. ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the o ther modes, in any serial reception (except see sm2). must be cleared by software. sm0 sm1 sm2 ren tb8 rb8 ti ri where sm0, sm1 specify the serial port mode, as follows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc /12 (12-clock mode) or f osc /6 (6-clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 (12-clock mode) or f osc /32 or f osc /16 (6-clock mode) 1 1 3 9-bit uart variable su01626 bit addressable scon address = 98h reset value = 00h 76543 210 figure 12. serial port control (scon) register baud rate f smod timer 1 mode 12-clock mode 6-clock mode f osc smod c/t mode reload value mode 0 max 1.67 mhz 3.34 mhz 20 mhz x x x x mode 2 max 625 k 1250 k 20 mhz 1 x x x mode 1, 3 max 104.2 k 208.4 k 20 mhz 1 0 2 ffh mode 1, 3 19.2 k 38.4 k 11.059 mhz 1 0 2 fdh 9.6 k 19.2 k 11.059 mhz 0 0 2 fdh 4.8 k 9.6 k 11.059 mhz 0 0 2 fah 2.4 k 4.8 k 11.059 mhz 0 0 2 f4h 1.2 k 2.4 k 11.059 mhz 0 0 2 e8h 137.5 275 11.986 mhz 0 0 2 1dh 110 220 6 mhz 0 0 2 72h 110 220 12 mhz 0 0 1 feebh figure 13. timer 1 generated commonly used baud rates more about mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or 1/6 the oscillator frequency (6-clock mode). figure 14 shows a simplified functional diagram of the serial port in mode 0, and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal at s6p2 also loads a 1 into the 9th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between awrite to sbufo and activation of send. send enables the output of the shift register to the alternate output function line of p3.0 and also enable shift clock to the alternate output function line of p3.1. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1, and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control block to do one last shift and then deactivate send and set t1. both of these actions occur at s1p1 of the 10th machine cycle after awrite to sbuf.o reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates receive. receive enable shift clock to the alternate output function line of p3.1. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the contents of the receive shift register are
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 23 shifted to the left one position. the value that comes in from the right is the value that was sampled at the p3.0 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared as ri is set. more about mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the 80c51 the baud rate is determined by the timer 1 or timer 2 overflow rate. figure 15 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit receive. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads a 1 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10th divide-by-16 rollover after awrite to sbuf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. r1 = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd. more about modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8) can be assigned the value of 0 or 1. on receive, the 9the data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1 or timer 2. figures 16 and 17 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads tb8 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. thereafter, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 11th divide-by-16 rollover after awrite to subf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of r-d. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. ri = 0, and 2. either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the first 8 data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 24 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send shift start s6 rx control start shift receive rx clock t1 r1 serial port interrupt 1 1 1 1 1 1 1 0 input shift register ren ri load sbuf shift shift clock rxd p3.0 alt output function txd p3.1 alt output function sbuf read sbuf 80c51 internal bus rxd p3.0 alt input function write to sbuf s6p2 send shift rxd (data out) d0 d1 d2 d3 d4 d5 d6 d7 transmit txd (shift clock) ti s3p1 s6p1 write to scon (clear ri) ri receive shift rxd (data in) d0 d1 d2 d3 d4 d5 d6 txd (shift clock) s5p2 receive d7 ale s4 . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 su00539 lsb lsb msb msb figure 14. serial port mode 0
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 25 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start rx clock ri t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 timer 1 overflow smod = 1 smod = 0 shift bit detector transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rxd rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data 16 load sbuf shift 1ffh su00540 figure 15. serial port mode 1
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 26 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start load sbuf rx clock t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 smod = 1 smod = 0 shift bit detector rxd stop bit gen. mode 2 phase 2 clock (1/2 f osc ) r1 16 shift 1ffh transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data (smod is pcon.7) tb8 rb8 stop bit gen. su00541 figure 16. serial port mode 2
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 27 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start rx clock t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 timer 1 overflow smod = 1 smod = 0 shift bit detector rxd r1 16 load sbuf shift 1ffh transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data tb8 rb8 stop bit gen. su00542 figure 17. serial port mode 3
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 28 enhanced uart in addition to the standard operation the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the uart also fully supports multiprocessor communication as does the standard 80c51 uart. when used for framing error detect the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6 (smod0) (see figure 18). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe scon.7 can only be cleared by software. refer to figure 19. automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 20. the 8 bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to b used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are trended as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0a9h) and saden (sfr address 0b9h) are leaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 29 scon address = 98h reset value = 0000 0000b sm0/fe sm1 sm2 ren tb8 rb8 tl rl bit addressable (smod0 = 0/1)* symbol function fe framing error bit. this bit is set by the receiver when an invalid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit. sm0 serial port mode bit 0, (smod0 must = 0 to access bit sm0) sm1 serial port mode bit 1 sm0 sm1 mode description baud rate** 0 0 0 shift register f osc /6 (6-clock mode) or f osc /12 (12-clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 or f osc /16 (6-clock mode) or f osc /64 or f osc /32 (12-clock mode) 1 1 3 9-bit uart variable sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then rl will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then rl will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. tl transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. rl receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. note: *smod0 is located at pcon6. **f osc = oscillator frequency su01255 bit: 76543210 figure 18. scon: serial port control register
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 30 smod1 smod0 pof lvf gf0 gf1 idl pcon (87h) sm0 / fe sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit set fe bit if stop bit is 0 (framing error) sm0 to uart mode control 0 : scon.7 = sm0 1 : scon.7 = fe su00044 figure 19. uart framing error detection sm0 sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. su00045 figure 20. uart multiprocessor communication, automatic address recognition
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 31 interrupt priority structure the p89c51ra2/rb2/rc2/rd2xx has a 7 source four-level interrupt structure (see table 7). there are 3 sfrs associated with the four-level interrupt. they are the ie, ip, and iph. (see figures 21, 22, and 23.) the iph (interrupt priority high) register makes the four-level interrupt structure possible. the iph is located at sfr address b7h. the structure of the iph register and a description of its bits is shown in figure 23. the function of the iph sfr, when combined with the ip sfr, determines the priority of each interrupt. the priority of each interrupt is determined as shown in the following table: priority bits interrupt priority level iph.x ip.x interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) the priority scheme for servicing the interrupts is the same as that for the 80c51, except there are four interrupt levels rather than two as on the 80c51. an interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. if an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. if a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. when the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. table 7. interrupt table source polling priority request bits hardware clear? vector address x0 1 ie0 n (l) 1 y (t) 2 03h t0 2 tp0 y 0bh x1 3 ie1 n (l) y (t) 13h t1 4 tf1 y 1bh pca 5 cf, ccfn n = 04 n 33h sp 6 ri, ti n 23h t2 7 tf2, exf2 n 2bh notes: 1. l = level activated 2. t = transition activated ex0 ie (0a8h) enable bit = 1 enables the interrupt. enable bit = 0 disables it. bit symbol function ie.7 ea global disable bit. if ea = 0, all interrupts are disabled. if ea = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. ie.6 ec pca interrupt enable bit ie.5 et2 timer 2 interrupt enable bit. ie.4 es serial port interrupt enable bit. ie.3 et1 timer 1 interrupt enable bit. ie.2 ex1 external interrupt 1 enable bit. ie.1 et0 timer 0 interrupt enable bit. ie.0 ex0 external interrupt 0 enable bit. su01290 et0 ex1 et1 es et2 ec ea 0 1 2 3 4 5 6 7 figure 21. ie registers
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 32 px0 ip (0b8h) priority bit = 1 assigns high priority priority bit = 0 assigns low priority bit symbol function ip.7 ip.6 ppc pca interrupt priority bit ip.5 pt2 timer 2 interrupt priority bit. ip.4 ps serial port interrupt priority bit. ip.3 pt1 timer 1 interrupt priority bit. ip.2 px1 external interrupt 1 priority bit. ip.1 pt0 timer 0 interrupt priority bit. ip.0 px0 external interrupt 0 priority bit. su01291 pt0 px1 pt1 ps pt2 ppc 0 1 2 3 4 5 6 7 figure 22. ip registers px0h iph (b7h) priority bit = 1 assigns higher priority priority bit = 0 assigns lower priority bit symbol function iph.7 iph.6 ppch pca interrupt priority bit iph.5 pt2h timer 2 interrupt priority bit high. iph.4 psh serial port interrupt priority bit high. iph.3 pt1h timer 1 interrupt priority bit high. iph.2 px1h external interrupt 1 priority bit high. iph.1 pt0h timer 0 interrupt priority bit high. iph.0 px0h external interrupt 0 priority bit high. su01292 pt0h px1h pt1h psh pt2h ppch 0 1 2 3 4 5 6 7 figure 23. iph registers
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 33 reduced emi mode the ao bit (auxr.0) in the auxr register when set disables the ale output unless the cpu needs to perform an off-chip memory access. reduced emi mode auxr (8eh) 765432 1 0 extram ao auxr.1 extram auxr.0 ao see more detailed description in figure 38. dual dptr the dual dptr structure (see figure 24) is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 that allows the program code to switch between them. ? new register name: auxr1# ? sfr address: a2h ? reset value: xxxxxxx0b auxr1 (a2h) 76 5 43210 enboot gf2 0 dps where: dps = auxr1/bit0 = switches between dptr0 and dptr1. select reg dps dptr0 0 dptr1 1 the dps bit status should be saved by software when switching between dptr0 and dptr1. the gf2 bit is a general purpose user-defined flag. note that bit 2 is not writable and is always read as a zero. this allows the dps bit to be quickly toggled simply by executing an inc auxr1 instruction without affecting the gf2 bit. the enboot bit determines whether the bootrom is enabled or disabled. this bit will automatically be set if the status byte is non zero during reset or psen is pulled low, ale floats high, and ea > v ih on the falling edge of reset. otherwise, this bit will be cleared during reset. dps dptr1 dptr0 dph (83h) dpl (82h) external data memory su00745a bit0 auxr1 figure 24. dptr instructions the instructions that refer to dptr refer to the data pointer that is currently selected using the auxr1/bit 0 register. the six instructions that use the dptr are as follows: inc dptr increments the data pointer by 1 mov dptr, #data16 loads the dptr with a 16-bit constant mov a, @ a+dptr move code byte relative to dptr to acc movx a, @ dptr move external ram (16-bit address) to acc movx @ dptr , a move acc to external ram (16-bit address) jmp @ a + dptr jump indirect relative to dptr the data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the sfrs. see application note an458 for more details.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 34 programmable counter array (pca) the programmable counter array available on the p89c51ra2/rb2/rc2/rd2xx is a special 16-bit timer that has five 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. each module has a pin associated with it in port 1. module 0 is connected to p1.3 (cex0), module 1 to p1.4 (cex1), etc. the basic pca configuration is shown in figure 25. the pca timer is a common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, the timer 0 overflow, or the input on the eci pin (p1.2). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr as follows (see figure 28): cps1 cps0 pca timer count source 0 0 1/6 oscillator frequency (6-clock mode); 1/12 oscillator frequency (12-clock mode) 0 1 1/2 oscillator frequency (6-clock mode); 1/4 oscillator frequency (12-clock mode) 1 0 timer 0 overflow 1 1 external input at eci pin in the cmod sfr are three additional bits associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function on module 4, and ecf which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. these functions are shown in figure 26. the watchdog timer function is implemented in module 4 (see figure 35). the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to figure 29). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set, the cf bit can only be cleared by software. bits 0 through 4 of the ccon register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. the pca interrupt system shown in figure 27. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see figure 30). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. figure 31 shows the ccapmn settings for the various pca functions. there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output. module functions: 16-bit capture 16-bit timer 16-bit high speed output 8-bit pwm watchdog timer (module 4 only) module 0 module 1 module 2 module 3 module 4 p1.3/cex0 p1.4/cex1 p1.5/cex2 p1.6/cex3 p1.7/cex4 16 bits pca timer/counter time base for pca modules 16 bits su00032 figure 25. programmable counter array (pca)
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 35 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (c0h) ch cl overflow interrupt 16bit up counter idle to pca modules cmod (c1h) cidl wdte cps1 cps0 ecf osc/6 (6 clock mode) or osc/12 (12 clock mode) timer 0 overflow external input (p1.2/eci) decode 00 01 10 11 su01256 osc/2 (6 clock mode) or osc/4 (12 clock mode) figure 26. pca timer/counter module 0 module 1 module 2 module 3 module 4 pca timer/counter cf cr ccf4 ccf3 ccf2 ccf1 ccf0 cmod.0 ecf ccapmn.0 eccfn to interrupt priority decoder ccon (c0h) ie.6 ec ie.7 ea su01097 figure 27. pca interrupt system
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 36 cmod address = d9h reset value = 00xx x000b cidl wdte cps1 cps0 ecf bit: symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. not implemented, reserved for future use.* cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input** 0 0 0 internal clock, f osc /6 in 6-clock mode (f osc /12 in 12-clock mode) 0 1 1 internal clock, f osc /2 in 6-clock mode (f osc /4 in 12-clock mode) 1 0 2 timer 0 overflow 1 1 3 external clock at eci/p1.2 pin (max. rate = f osc /4 in 6-clock mode, f ocs /8 in 12-clock mode) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function of cf. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ** f osc = oscillator frequency su01318 76543210 figure 28. cmod: pca counter mode register ccon address = d8h reset value = 00x0 0000b cf cr ccf4 ccf3 ccf2 ccf1 ccf0 bit addressable bit: symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. not implemented, reserved for future use*. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01319 76543210 figure 29. ccon: pca counter control register
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 37 ccapmn address ccapm0 0dah ccapm1 0dbh ccapm2 0dch ccapm3 0ddh ccapm4 0deh reset value = x000 0000b ecomn cappn capnn matn togn pwmn eccfn not bit addressable bit: symbol function not implemented, reserved for future use*. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01320 76543210 figure 30. ccapmn: pca modules compare/capture registers ecomn cappn capnn matn togn pwmn eccfn module function x 0 0 0 0 0 0 0 no operation x x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x x 0 1 0 0 0 x 16-bit capture by a negative trigger on cexn x x 1 1 0 0 0 x 16-bit capture by a transition on cexn x 1 0 0 1 0 0 x 16-bit software timer x 1 0 0 1 1 0 x 16-bit high speed output x 1 0 0 0 0 1 0 8-bit pwm x 1 0 0 1 x 0 x watchdog timer figure 31. pca module modes (ccapmn register) pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated. refer to figure 32. 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 33). high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 34). pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 35 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. the allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 38 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (dah deh) ch cl ccapnh ccapnl cexn capture pca interrupt pca timer/counter 0 000 (to ccfn) su01608 figure 32. pca capture mode match cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (dah deh) ch cl ccapnh ccapnl pca interrupt pca timer/counter 00 00 16bit comparator (to ccfn) enable write to ccapnh reset write to ccapnl 01 su01609 figure 33. pca compare mode
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 39 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (dah deh) ch cl ccapnh ccapnl pca interrupt pca timer/counter 10 00 16bit comparator (to ccfn) write to ccapnh reset write to ccapnl 01 enable cexn toggle match su01610 figure 34. pca high speed output mode cl < ccapnl ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (dah deh) pca timer/counter 00 00 cl ccapnl cexn 8bit comparator overflow ccapnh enable 0 1 cl >= ccapnl 0 su01611 figure 35. pca pwm mode
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 40 ecomn cappn capnn matn togn pwmn eccfn ccapm4 (deh) ch cl ccap4h ccap4l reset pca timer/counter x0 00 16bit comparator match enable write to ccap4l reset write to ccap4h 10 1 cmod (d9h) cidl wdte cps1 cps0 ecf x su01612 module 4 figure 36. pca watchdog timer mode (module 4 only) pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 36 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer, 2. periodically change the pca timer value so it will never match the compare values, or 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the first solution is the best option. figure 37 shows the code for initializing the watchdog timer. module 4 can be configured in either compare mode, and the wdte bit in cmod must also be set. the user's software then must periodically change (ccap4h,ccap4l) to keep a match from occurring with the pca timer (ch,cl). this code is given in the watchdog routine in figure 37. this routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. thus, the purpose of the watchdog would be defeated. instead, call this subroutine from the main program within 2 16 count of the pca timer.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 41 init_watchdog: mov ccapm4, #4ch ; module 4 in compare mode mov ccap4l, #0ffh ; write to low byte first mov ccap4h, #0ffh ; before pca timer counts up to ; ffff hex, these compare values ; must be changed orl cmod, #40h ; set the wdte bit to enable the ; watchdog timer without changing ; the other bits in cmod ; ;******************************************************************** ; ; main program goes here, but call watchdog periodically. ; ;******************************************************************** ; watchdog: clr ea ; hold off interrupts mov ccap4l, #00 ; next compare value is within mov ccap4h, ch ; 255 counts of the current pca setb ea ; timer value ret figure 37. pca watchdog timer initialization code
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 42 expanded data ram addressing the p89c51ra2/rb2/rc2/rd2xx has internal data memory that is mapped into four separate segments: the lower 128 bytes of ram, upper 128 bytes of ram, 128 bytes special function register (sfr), and 256 bytes expanded ram (eram) (768 bytes for the rd2xx). the four segments are: 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. 3. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. 4. the 256/768-bytes expanded ram (eram, 00h 1ffh/2ffh) are indirectly accessed by move external instruction, movx, and with the extram bit cleared, see figure 38. the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically separate from sfr space. when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. instructions that use direct addressing access sfr space. for example: mov 0a0h,#data accesses the sfr at location 0a0h (which is p2). instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0,acc where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). the eram can be accessed by indirect addressing, with extram bit cleared and movx instructions. this part of memory is physically located on-chip, logically occupies the first 256/768 bytes of external data memory in the p89c51ra2/rb2/rc2/89c51rd2. with extram = 0, the eram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to eram will not affect ports p0, p3.6 (wr#) and p3.7 (rd#). p2 sfr is output during external addressing. for example, with extram = 0, movx @r0,acc where r0 contains 0a0h, accesses the eram at address 0a0h rather than external memory. an access to external data memory locations higher than the eram will be performed with the movx dptr instructions in the same way as in the standard 80c51, so with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. refer to figure 39. with extram = 1, movx @ri and movx @dptr will be similar to the standard 80c51. movx @ ri will provide an 8-bit address multiplexed with data on port 0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @dptr will generate a 16-bit address. port 2 outputs the high-order eight address bits (the contents of dph) while port 0 multiplexes the low-order eight address bits (dpl) with data. movx @ri and movx @dptr will generate either read or write signals on p3.6 (wr ) and p3.7 (rd ). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may not be located in the eram. auxr reset value = xxxx xx00b e eeeee extram ao not bit addressable bit: symbol function ao disable/enable ale ao operating mode 0 ale is emitted at a constant rate of 1 / 6 the oscillator frequency (12-clock mode; 1 / 3 f osc in 6-clock mode). 1 ale is active only during off-chip memory access. extram internal/external ram access using movx @ri/@dptr extram operating mode 0 internal eram access using movx @ri/@dptr 1 external data memory access. e not implemented, reserved for future use*. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01613 76543210 address = 8eh figure 38. auxr: auxiliary register
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 43 eram 256 or 768 bytes upper 128 bytes internal ram lower 128 bytes internal ram special function register 100 ff 00 ff 00 80 80 external data memory ffff 0000 su01293 figure 39. internal and external data memory address space with extram = 0 hardware watchdog timer (one-time enabled with reset-out for p89c51ra2/rb2/rc2/rd2xx) the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is disabled at reset. to enable the wdt, the user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when the wdt is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when the wdt overflows, it will drive an output reset high pulse at the rst-pin (see the note below). using the wdt to enable the wdt, the user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when the wdt is enabled, the user needs to service it by writing 01eh and 0e1h to wdtrst to avoid a wdt overflow. the 14-bit counter overflows when it reaches 16383 (3fffh) and this will reset the device. when the wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycles. to reset the wdt, the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when the wdt overflows, it will generate an output reset pulse at the reset pin (see note below). the reset pulse duration is 98 t osc (6-clock mode; 196 in 12-clock mode), where t osc = 1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 44 flash eprom memory general description the p89c51ra2/rb2/rc2/rd2xx flash memory augments eprom functionality with in-circuit electrical erasure and programming. the flash can be read and written as bytes. the chip erase operation will erase the entire program memory. the block erase function can erase any flash block. in-system programming and standard parallel programming are both available. on-chip erase and write timing generation contribute to a user friendly programming interface. the p89c51ra2/rb2/rc2/rd2xx flash reliably stores memory contents even after 10,000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the p89c51ra2/rb2/rc2/rd2xx uses a +5 v v pp supply to perform the program/erase algorithms. features in-system programming (isp) and in-application programming (iap) ? flash eprom internal program memory with block erase. ? internal 1-kbyte fixed bootrom, containing low-level in-system programming routines and a default serial loader. user program can call these routines to perform in-application programming (iap). the bootrom can be turned off to provide access to the full 64-kbyte flash memory. ? boot vector allows user provided flash loader code to reside anywhere in the flash memory space. this configuration provides flexibility to the user. ? default loader in bootrom allows programming via the serial port without the need for a user provided loader. ? up to 64-kbyte external program memory if the internal program memory is disabled (ea = 0). ? programming and erase voltage +5 v (+12 v tolerant). ? read/programming/erase using isp/iap: byte programming (8 s). typical quick erase times: block erase (4 kbyte) in 3 seconds. full chip erase: rd2xx (64k) in 11 seconds rc2 (32k) in 7 seconds rb2 (16k) in 5 seconds ra2 (4k) in 4 seconds ? parallel programming with 87c51 compatible hardware interface to programmer. ? in-system programming (isp). ? in-application programming (iap). ? programmable security for the code in the flash. ? 10,000 minimum erase/program cycles for each byte. ? 10-year minimum data retention. flash programming and erasure in general, there are three methods of erasing or programming of the flash memory that may be used. first, the flash may be programmed or erased in the end-user application by calling low-level routines through entry point in the bootrom. the end-user application, though, must be executing code from a different block than the block that is being erased or programmed. second, the on-chip isp boot loader may be invoked. this isp boot loader will, in turn, call low-level routines through the common entry point in the bootrom that can be used by end-user applications. third, the flash may be programmed or erased using parallel method by using a commercially available eprom programmer. the parallel programming method used by these devices is similar to that used by eprom 87c51, but it is not identical, and the commercially available programmer will need to have support for these devices. flash memory spaces flash user code memory organization the p89c51ra2/rb2/rc2/rd2xx contains 8kb/16kb/32kb/64kb flash user code program memory organized into 4-kbyte blocks. isp and iap bootrom routines will support the new 4-kbyte block sizes through additional block number assignments while maintaining compatibility with previous 8-kbyte and 16-kbyte block assignments. this memory space is programmable via iap, isp, and parallel modes. status byte/boot vector block this device includes a 4-kbyte block which contains the status byte and boot vector (status byte block) . the status byte and boot vector are programmable via iap, isp, and parallel modes. note that erasing of either the status byte and boot vector will erase the entire contents of this block. thus the status byte and boot vector are erased together but are programmable separately. security & user configuration block this device includes a 4-kbyte block (security block) which contains the security bits, the 6-clock/12-clock flash-based clock mode bit fx2, and 4095 user programmable bytes. this block is programmable via iap, isp, and parallel modes. security bits will prevent, as required, parallel programmers from reading or writing, however, iap or isp inhibitions will be software controlled. this block may only be erased using full-chip erase functions in isp, iap, or parallel mode. this security feature protects against software piracy and prevents the contents of the flash from being read. the security bits are located in the flash. there are three programmable security bits that will provide different levels of protection for the on-chip code and data (see table 11). the 4095 user programmable bytes are not part of user code memory are intended to be programmed or read through iap, isp, or parallel programmer functions. the 6-clock/12-clock flash-based clock mode bit fx2 will be latched at power-on. this allows the bit to be changed via iap or isp and delay taking effect until the next reset. this avoids changing baud rates during isp operations. boot rom when the microcontroller programs its flash memory, all of the low level details are handled by code that is contained in a 1-kbyte
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 45 bootrom that is shadowed over a portion of the user code memory space. a user program simply calls the common entry point with appropriate parameters in the bootrom to accomplish the desired operation. bootrom operations include: erase block, program byte, verify byte, program security bit, etc. the bootrom overlays the program memory space at the top of the address space from fc00 to ffff hex, when it is enabled. the bootrom may be turned off so that the upper 1 kbyte of user program memory is accessible for execution. clock mode the clock mode feature sets operating frequency to be 1/12 or 1/6 of the oscillator frequency. the clock mode configuration bit, fx2, is located in the security block (see table 8). fx2, when programmed, will override the sfr clock mode bit (x2) in the ckcon register. if fx2 is erased, then the sfr bit (x2) may be used to select between 6-clock and 12-clock mode. table 8. clock mode config bit (fx2) x2 bit in ckcon description erased 0 12-clock mode (default) erased 1 6-clock mode programmed x 6-clock mode note: 1. default clock mode after chiperase is set to sfr selection. flash memory spaces flash user code memory organization ffff c000 8000 4000 2000 0000 program address boot rom (1 kb) ffff fc00 su01614 89c51rd2xx 89c51rc2xx 89c51rb2xx 89c51ra2xx block 1 block 0 block 3 block 2 block 5 block 4 block 7 block 6 block 9 block 8 block 11 block 10 block 13 block 12 block 15 block 14 each block is 4 kbytes in size figure 40. flash memory configurations power-on reset code execution the p89c51ra2/rb2/rc2/rd2xx contains two special flash registers: the boot vector and the status byte. at the falling edge of reset, the p89c51ra2/rb2/rc2/rd2xx examines the contents of the status byte. if the status byte is set to zero, power-up execution starts at location 0000h, which is the normal start address of the user's application code. when the status byte is set to a value other than zero, the contents of the boot vector is used as the high byte of the execution address and the low byte is set to 00h. the factory default setting is 0fch, corresponds to the address 0fc00h for the factory masked-rom isp boot loader. a custom boot loader can be written with the boot vector set to the custom boot loader. note: when erasing the status byte or boot vector, both bytes are erased at the same time. it is necessary to reprogram the boot vector after erasing and updating the status byte.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 46 hardware activation of the boot loader the boot loader can also be executed by holding psen low, ea greater than v ih (such as +5 v), and ale high (or not connected) at the falling edge of reset. this is the same effect as having a non-zero status byte. this allows an application to be built that will normally execute the end user's code but can be manually forced into isp operation. if the factory default setting for the boot vector (0fch) is changed, it will no longer point to the isp masked-rom boot loader code. if this happens, the only way it is possible to change the contents of the boot vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the boot vector and status byte. after programming the flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000h. +5 v (+12 v tolerant) +5 v txd rxd v ss v pp v cc txd rxd rst xtal2 xtal1 su01615 v ss v cc p89c51ra2xx P89C51RB2xx p89c51rc2xx p89c51rd2xx figure 41. in-system programming with a minimum of pins in-system programming (isp) the in-system programming (isp) is performed without removing the microcontroller from the system. the in-system programming (isp) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the p89c51ra2/rb2/rc2/rd2xx through the serial port. this firmware is provided by philips and embedded within each p89c51ra2/rb2/rc2/rd2xx device. the philips in-system programming (isp) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses five pins: txd, rxd, v ss , v cc , and v pp (see figure 41). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. the v pp supply should be adequately decoupled and v pp not allowed to exceed datasheet limits. free isp software is available from the embedded systems academy: aflashmagico 1. direct your browser to the following page: http://www.esacademy.com/software/flashmagic/ 2. download flashmagic 3. execute aflashmagic.exeo to install the software using the in-system programming (isp) the isp feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. it is also adaptable to a wide range of oscillator frequencies. this is accomplished by measuring the bit-time of a single bit in a received character. this information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. the isp feature requires that an initial character (an uppercase u) be sent to the p89c51ra2/rb2/rc2/rd2xx to establish the baud rate. the isp firmware provides auto-echo of received characters. once baud rate initialization has been performed, the isp firmware will only accept intel hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below: :nnaaaarrdd..ddcc in the intel hex record, the anno represents the number of data bytes in the record. the p89c51ra2/rb2/rc2/rd2xx will accept up to 16 (10h) data bytes. the aaaaao string represents the address of the first byte in the record. if there are zero bytes in the record, this field is often set to 0000. the arro string indicates the record type. a record type of a00o is a data record. a record type of a01o indicates the end-of-file mark. in this application, additional record types will be added to indicate either commands or data for the isp facility. the maximum number of data bytes in a record is limited to 16 (decimal). isp commands are summarized in table 9. as a record is received by the p89c51ra2/rb2/rc2/rd2xx, the information in the record is stored internally and a checksum calculation is performed. the operation indicated by the record type is not performed until the entire record has been received. should an error occur in the checksum, the p89c51ra2/rb2/rc2/rd2xx will send an axo out the serial port indicating a checksum error. if the checksum calculation is found to match the checksum in the record, then the command will be executed. in most cases, successful reception of the record will be indicated by transmitting a a.o character out the serial port (displaying the contents of the internal program memory is an exception). in the case of a data record (record type 00), an additional check is made. a a.o character will not be sent unless the record checksum matched the calculated checksum and all of the bytes in the record
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 47 were successfully programmed. for a data record, an axo indicates that the checksum failed to match, and an aro character indicates that one of the bytes did not properly program. it is necessary to send a type 02 record (specify oscillator frequency) to the p89c51ra2/rb2/rc2/rd2xx before programming data. the isp facility was designed to that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses. the user thus needs to provide the p89c51ra2/rb2/rc2/rd2xx with information required to generate the proper timing. record type 02 is provided for this purpose.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 48 table 9. intel-hex records used by in-system programming record type command/data function 00 program data :nnaaaa00dd....ddcc where: nn = number of bytes (hex) in record aaaa = memory address of first byte in record dd....dd = data bytes cc = checksum example: :10008000af5f67f0602703e0322cfa92007780c3fd 01 end of file (eof), no operation :xxxxxx01cc where: xxxxxx = required field, but value is a adon't careo cc = checksum example: :00000001ff 03 miscellaneous write functions :nnxxxx03ffssddcc where: nn = number of bytes (hex) in record xxxx = required field, but value is a adon't careo 03 = write function ff = subfunction code ss = selection code dd = data input (as needed) cc = checksum subfunction code = 01 (erase 8k/16k code blocks) ff = 01 ss = block code as shown below: block 0, 0k to 8k, 00h block 1, 8k to 16k, 20h (rb2, rc2, rd2) block 2, 16k to 32k, 40h (rc2, rd2) block 3, 32k to 48k, 80h (rd2 only) block 4, 48k to 64k, c0h (rd2 only) example: :0200000301c03a erase block 4 subfunction code = 04 (erase boot vector and status byte) ff = 04 ss = don't care example: :020000030400f7 erase boot vector and status byte subfunction code = 05 (program security bits) ff = 05 ss = 00 program security bit 1 (inhibit writing to flash) 01 program security bit 2 (inhibit flash verify) 02 program security bit 3 (disable external memory) example: :020000030501f5 program security bit 2 subfunction code = 06 (program status byte or boot vector) ff = 06 ss = 00 program status byte 01 program boot vector 02 program fx2 bit (dd = 80) dd = data example 1: :030000030601fcf7 program boot vector with 0fch example 2: :0300000306028072 program fx2 bit (select 12-clock mode)
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 49 record type command/data function 03 (cont.) subfunction code = 07 (full chip erase) erases all blocks, security bits, and sets status byte and boot vector to default values ff = 07 ss = don't care dd = don't care example: :0100000307f5 full chip erase subfunction code = 0c (erase 4k blocks) ff = 0c ss = block code as shown below: block 0 , 0k~4k , 00h block 1 , 4k~8k , 10h block 2 , 8k~12k , 20h (only available on rd2 / rc2 / rb2) block 3 , 12k~16k , 30h (only available on rd2 / rc2 / rb2) block 4 , 16k~20k , 40h (only available on rd2 / rc2) block 5 , 20k~24k , 50h (only available on rd2 / rc2) block 6 , 24k~28k , 60h (only available on rd2 / rc2) block 7 , 28k~32k , 70h (only available on rd2 / rc2) block 8 , 32k~36k , 80h (only available on rd2) block 9 , 36k~40k , 90h (only available on rd2) block 10, 40k~44k , a0h (only available on rd2) block 11, 44k~48k , b0h (only available on rd2) block 12, 48k~52k , c0h (only available on rd2) block 13, 52k~56k , d0h (only available on rd2) block 14, 56k~60k , e0h (only available on rd2) block 15, 60k~64k , f0h (only available on rd2) example: :020000030c20cf (erase 4k block #2) 04 display device data or blank check record type 04 causes the contents of the entire flash array to be sent out the serial port in a formatted display. this display consists of an address and the contents of 16 bytes starting with that address. no display of the device contents will occur if security bit 2 has been programmed. data to the serial port is initiated by the reception of any character and terminated by the reception of any character. general format of function 04 :05xxxx04sssseeeeffcc where: 05 = number of bytes (hex) in record xxxx = required field, but value is a adon't careo 04 = adisplay device data or blank checko function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check 02 = display data in data block (valid addresses: 0001~0fffh) cc = checksum example 1: :0500000440004fff0069 display 40004fff example 2: :0500000400000fff02e7 display data in data block (the data at address 0000 is invalid)
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 50 record type command/data function 05 miscellaneous read functions (selection) general format of function 05 :02xxxx05ffsscc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a adon't careo 05 = amiscellaneous reado function code ffss = subfunction and selection code 0000 = read signature byte manufacturer id (15h) 0001 = read signature byte device id # 1 (c2h) 0002 = read signature byte device id # 2 0003 = read fx2 bit 0080 = read rom code revision 0700 = read security bits 0701 = read status byte 0702 = read boot vector cc = checksum example 1: :020000050001f8 read signature byte device id # 1 example 2: :020000050003f6 read fx2 bit (bit7=0 represent 12clock mode, bit7=1 represent 6clock mode) example 3: :02000005008079 read rom code revision (0a: rev. a, 0b:rev. b) 06 direct load of baud rate general format of function 06 :02xxxx06hhllcc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a adon't careo 06 = odirect load of baud rateo function code hh = high byte of timer 2 ll = low byte of timer 2 cc = checksum example: :02000006f500f3 07 program data in data block :nnaaaa07dd....ddcc where: nn = number of bytes (hex) in record aaaa = memory address of first byte in record (the valid address:0001~0fffh) dd....dd = data bytes cc = checksum example: :10008007af5f67f0602703e0322cfa92007780c3f6
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 51 in application programming method several in application programming (iap) calls are available for use by an application program to permit selective erasing and programming of flash sectors. all calls are made through a common interface, pgm_mtp. the programming functions are selected by setting up the microcontroller's registers before making a call to pgm_mtp at fff0h. the oscillator frequency is an integer number rounded down to the nearest megahertz. for example, set r0 to 11 for 11.0592 mhz. results are returned in the registers. the iap calls are shown in table 10. using the watchdog timer (wdt) the p89c51rx2 devices support the use of the wdt in iap. the user specifies that the wdt is to be fed by setting the most significant bit of the function parameter passed in r1 prior to calling pgm_mtp. the wdt function is only supported for block erase when using quick block erase. the quick block erase is specified by performing a block erase with register r0 = 0. requesting a wdt feed during iap should only be performed in applications that use the wdt since the process of feeding the wdt will start the wdt if the wdt was not running. table 10. iap calls iap call parameter program byte input parameter: r0 = osc freq (integer) r1 = 02h or r1= 82h (wdt feed) dptr = address of byte to program acc = byte to program return parameter: acc = 00 if pass, !=00 if fail erase 4k code block (new function) input parameter: r0 = osc freq (integer) r1 = 0ch or r1 = 8ch (wdt feed) dph = address of 4k code block dph = 00h , 4k block 0, 0k~4k dph = 10h , 4k block 1, 4k~8k dph = 20h , 4k block 2, 8k~12k dph = 30h , 4k block 3, 12k~16k dph = 40h , 4k block 4, 16k~20k dph = 50h , 4k block 5, 20k~24k dph = 60h , 4k block 6, 24k~28k dph = 70h , 4k block 7, 28k~32k dph = 80h , 4k block 8, 32k~36k dph = 90h , 4k block 9, 36k~40k dph = a0h , 4k block 10, 40k~44k dph = b0h , 4k block 11, 44k~48k dph = c0h , 4k block 12, 48k~52k dph = d0h , 4k block 13, 52k~56k dph = e0h , 4k block 14, 56k~60k dph = f0h , 4k block 15, 60k~64k dpl = 00h return parameter: acc = 00 if pass, !=00 if fail erase 8k / 16k code block input parameter: r0 = osc freq (integer) r1 = 01h or r1 = 81h (wdt feed) dph = address of code block dph = 00h , block 0 , 0k~8k dph = 20h , block 1 , 8k~16k dph = 40h , block 2 , 16~32k dph = 80h , block 3 , 32k~48k dph = c0h , block 4 , 48k~64k dpl = 00h return parameter: acc = 00 if pass , !=0 if fail erase status byte & boot vector input parameter: r0 = osc freq (integer) r1 = 04h or r1 = 84h (wdt feed) dph = 00h dpl = don't care return parameter: acc = 00 if pass , !=0 if fail
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 52 iap call parameter program security bits input parameter: r0 = osc freq (integer) r1 = 05h or r1 = 85h (wdt feed) dph = 00h dpl = 00h , security bit #1 dpl = 01h , security bit #2 dpl = 02h , security bit #3 return parameter: acc = 00 if pass , !=0 if fail program status byte input parameter: r0 = osc freq (integer) r1 = 06h or r1 = 86h (wdt feed) dph = 00h dpl = 00h - program status byte acc = status byte return parameter: acc = 00 if pass , !=0 if fail program boot vector input parameter: r0 = osc freq (integer) r1 = 06h or r1 = 86h (wdt feed) dph = 00h dpl = 01h - program boot vector acc = boot vector return parameter: acc = 00 if pass , !=0 if fail program 6clk/12clk configuration bit (new function) input parameter: r0 = osc freq (integer) r1 = 06h or r1 = 86h (wdt feed) dph = 00h dpl = 02h - program config bit acc = 80h (msb = 6clk/12clk bit) return parameter: acc = 00 if pass , !=0 if fail program data block (new function) input parameter: r0 = osc freq (integer) r1 = 0dh or r1 = 8dh (wdt feed) dptr = address of byte to program (valid addresses = 0001h~0fffh) acc = data return parameter: acc = 00 if pass , !=0 if fail read device data input parameter: r0 = osc freq (integer) r1 = 03h or r1 = 83h (wdt feed) dptr = address of byte to read return parameter: acc = value of byte read read data block (new function) input parameter: r0 = osc freq (integer) r1 = 0eh or r1 = 8eh (wdt feed) dptr = address of byte to read (valid addresses = 0001h~0fffh) return parameter: acc = value of byte read read manufacturer id input parameter: r0 = osc freq (integer) r1 = 00h or r1 = 80h (wdt feed) dph = 00h dpl = 00h - read manufacturer id return parameter: acc = value of byte read
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 53 iap call parameter read device id #1 input parameter: r0 = osc freq (integer) r1 = 00h or r1 = 80h (wdt feed) dph = 00h dpl = 01h - read device id #1 return parameter: acc = value of byte read read device id #2 input parameter: r0 = osc freq (integer) r1 = 00h or r1 = 80h (wdt feed) dph = 00h dpl = 02h - read device id #2 return parameter: acc = value of byte read read security bits input parameter: r0 = osc freq (integer) r1 = 07h or r1 = 87h (wdt feed) dph = 00h dpl = 00h - read lock byte return parameter: acc = value of byte read read status byte input parameter: r0 = osc freq (integer) r1 = 07h or r1 = 87h (wdt feed) dph = 00h dpl = 01h - read status byte return parameter: acc = value of byte read read boot vector input parameter: r0 = osc freq (integer) r1 = 07h or r1 = 87h (wdt feed) dph = 00h dpl = 02h - read boot vector return parameter: acc = value of byte read read config (new function) input parameter: r0 = osc freq (integer) r1 = 00h or r1 = 80h (wdt feed) dph = 00h dpl = 03h - read config byte return parameter: acc = value of byte read read revision (new function) input parameter: r0 = osc freq (integer) r1 = 00h or r1 = 80h (wdt feed) dph = 00h dpl = 80h - read revision of rom code return parameter: acc = value of byte read
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 54 security the security feature protects against software piracy and prevents the contents of the flash from being read. the security lock bits are located in flash. the p89c51ra2/rb2/rc2/rd2xx has three programmable security lock bits that will provide different levels of protectio n for the on-chip code and data (see table 11). table 11. security lock bits 1 protection description level lb1 lb2 lb3 protection description 1 0 0 0 movc instructions executed from external program memory are disabled from fetching code bytes from internal memory. 2 1 0 0 block erase is disabled. erase or programming of the status byte or boot vector is disabled. 3 1 1 0 verify of code memory is disabled. 4 1 1 1 external execution is disabled. note: 1. security bits are independent of each other. full-chip erase may be performed regardless of the state of the security bits. 2. any other combination of lock bits is undefined. 3. setting lbx doesn't prevent programming of unprogrammed bits.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 55 absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 0 to +70 or 40 to +85 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to +6.5 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 56 dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c; v cc = 5 v 10%; v ss = 0 v symbol parameter test limits unit symbol parameter conditions min typ 1 max unit v il input low voltage 4.5 v < v cc < 5.5 v 0.5 0.2v cc 0.1 v v ih input high voltage (ports 0, 1, 2, 3, ea ) 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 0.7v cc v cc +0.5 v v ol output low voltage, ports 1, 2, 3 8 v cc = 4.5 v i ol = 1.6 ma 2 0.4 v v ol1 output low voltage, port 0, ale, psen 7, 8 v cc = 4.5 v i ol = 3.2 ma 2 0.45 v v oh output high voltage, ports 1, 2, 3 3 v cc = 4.5 v i oh = 30 m a v cc 0.7 v v oh1 output high voltage (port 0 in external bus mode), ale 9 , psen 3 v cc = 4.5 v i oh = 3.2 ma v cc 0.7 v i il logical 0 input current, ports 1, 2, 3 v in = 0.4 v 1 75 m a i tl logical 1-to-0 transition current, ports 1, 2, 3 6 v in = 2.0 v see note 4 650 m a i li input leakage current, port 0 0.45 < v in < v cc 0.3 10 m a i cc power supply current (see figure 49): see note 5 active mode (see note 5) idle mode (see note 5) power-down mode or clock stopped (see fi 55 f diti ) t amb = 0 c to 70 c < 30 100 m a figure 55 for conditions) t amb = 40 c to +85 c < 40 125 m a programming and erase mode f osc = 20 mhz 60 ma r rst internal reset pull-down resistor 40 225 k w c io pin capacitance 10 (except ea ) 15 pf notes: 1. typical ratings are not guaranteed. the values listed are at room temperature, 5 v. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper ations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5 ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v cc 0.7 specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is approximately 2 v. 5. see figures 52 through 55 for i cc test conditions and figure 49 for i cc vs freq. active mode: i cc(max) = (10.5 + 0.9 freq.[mhz])ma in 12-clock mode idle mode: i cc(max) = (2.5 + 0.33 freq.[mhz])ma in 12-clock mode 6. this value applies to t amb = 0 c to +70 c. 7. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma (*note: this is 85 c specification.) maximum i ol per 8-bit port: 26 ma maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. ale is tested to v oh1 , except when ale is off then v oh is the voltage specification. 10. pin capacitance is characterized but not tested. pin capacitance is less than 25 pf. pin capacitance of ceramic package is l ess than 15 pf (except ea is 25 pf).
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 57 ac electrical characteristics (12-clock mode) t amb = 0 c to +70 c or 40 c to +85 c; v cc = 5 v 10%, v ss = 0 v 1, 2, 3 variable clock 4 33 mhz clock 4 symbol figure parameter min max min max unit 1/t clcl 42 oscillator frequency 0 33 mhz t lhll 42 ale pulse width 2t clcl 40 21 ns t avll 42 address valid to ale low t clcl 25 5 ns t llax 42 address hold after ale low t clcl 25 5 ns t lliv 42 ale low to valid instruction in 4t clcl 65 55 ns t llpl 42 ale low to psen low t clcl 25 5 ns t plph 42 psen pulse width 3t clcl 45 45 ns t pliv 42 psen low to valid instruction in 3t clcl 60 30 ns t pxix 42 input instruction hold after psen 0 0 ns t pxiz 42 input instruction float after psen t clcl 25 5 ns t aviv 42 address to valid instruction in 5t clcl 80 70 ns t plaz 42 psen low to address float 10 10 ns data memory t rlrh 43, 44 rd pulse width 6t clcl 100 82 ns t wlwh 43, 44 wr pulse width 6t clcl 100 82 ns t rldv 43, 44 rd low to valid data in 5t clcl 90 60 ns t rhdx 43, 44 data hold after rd 0 0 ns t rhdz 43, 44 data float after rd 2t clcl 28 32 ns t lldv 43, 44 ale low to valid data in 8t clcl 150 90 ns t avdv 43, 44 address to valid data in 9t clcl 165 105 ns t llwl 43, 44 ale low to rd or wr low 3t clcl 50 3t clcl +50 40 140 ns t avwl 43, 44 address valid to wr low or rd low 4t clcl 75 45 ns t qvwx 43, 44 data valid to wr transition t clcl 30 0 ns t whqx 43, 44 data hold after wr t clcl 25 5 ns t qvwh 44 data valid to wr high 7t clcl 130 80 ns t rlaz 43, 44 rd low to address float 0 0 ns t whlh 43, 44 rd or wr high to ale high t clcl 25 t clcl +25 5 55 ns external clock t chcx 46 high time 17 t clcl t clcx ns t clcx 46 low time 17 t clcl t chcx ns t clch 46 rise time 5 ns t chcl 46 fall time 5 ns shift register t xlxl 45 serial port clock cycle time 12t clcl 360 ns t qvxh 45 output data setup to clock rising edge 10t clcl 133 167 ns t xhqx 45 output data hold after clock rising edge 2t clcl 80 50 ns t xhdx 45 input data hold after clock rising edge 0 0 ns t xhdv 45 clock rising edge to input data valid 10t clcl 133 167 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 3. interfacing the microcontroller to devices with float times up to 45 ns is permitted. this limited bus contention will not ca use damage to port 0 drivers. 4. parts are tested to 3.5 mhz, but guaranteed to operate down to 0 hz.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 58 ac electrical characteristics (6-clock mode) t amb = 0 c to +70 c or 40 c to +85 c; v cc = 5 v 10%, v ss = 0 v 1, 2, 3 variable clock 4 20 mhz clock 4 symbol figure parameter min max min max unit 1/t clcl 42 oscillator frequency 0 20 mhz t lhll 42 ale pulse width t clcl 40 10 ns t avll 42 address valid to ale low 0.5t clcl 20 5 ns t llax 42 address hold after ale low 0.5t clcl 20 5 ns t lliv 42 ale low to valid instruction in 2t clcl 65 35 ns t llpl 42 ale low to psen low 0.5t clcl 20 5 ns t plph 42 psen pulse width 1.5t clcl 45 30 ns t pliv 42 psen low to valid instruction in 1.5t clcl 60 15 ns t pxix 42 input instruction hold after psen 0 0 ns t pxiz 42 input instruction float after psen 0.5t clcl 20 5 ns t aviv 42 address to valid instruction in 2.5t clcl 80 45 ns t plaz 42 psen low to address float 10 10 ns data memory t rlrh 43, 44 rd pulse width 3t clcl 100 50 ns t wlwh 43, 44 wr pulse width 3t clcl 100 50 ns t rldv 43, 44 rd low to valid data in 2.5t clcl 90 35 ns t rhdx 43, 44 data hold after rd 0 0 ns t rhdz 43, 44 data float after rd t clcl 20 5 ns t lldv 43, 44 ale low to valid data in 4t clcl 150 50 ns t avdv 43, 44 address to valid data in 4.5t clcl 165 60 ns t llwl 43, 44 ale low to rd or wr low 1.5t clcl 50 1.5t clcl +50 25 125 ns t avwl 43, 44 address valid to wr low or rd low 2t clcl 75 25 ns t qvwx 43, 44 data valid to wr transition 0.5t clcl 25 0 ns t whqx 43, 44 data hold after wr 0.5t clcl 20 5 ns t qvwh 44 data valid to wr high 3.5t clcl 130 45 ns t rlaz 43, 44 rd low to address float 0 0 ns t whlh 43, 44 rd or wr high to ale high 0.5t clcl 20 0.5t clcl +20 5 45 ns external clock t chcx 46 high time 20 t clcl t clcx ns t clcx 46 low time 20 t clcl t chcx ns t clch 46 rise time 5 ns t chcl 46 fall time 5 ns shift register t xlxl 45 serial port clock cycle time 6t clcl 300 ns t qvxh 45 output data setup to clock rising edge 5t clcl 133 117 ns t xhqx 45 output data hold after clock rising edge t clcl 30 20 ns t xhdx 45 input data hold after clock rising edge 0 0 ns t xhdv 45 clock rising edge to input data valid 5t clcl 133 117 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 3. interfacing the microcontroller to devices with float times up to 45 ns is permitted. this limited bus contention will not ca use damage to port 0 drivers. 4. parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz.
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 59 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 42. external program memory read cycle ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00025 figure 43. external data memory read cycle
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 60 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx t qvwh su00026 figure 44. external data memory write cycle 012345678 instruction ale clock output data write to sbuf input data clear ri set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 valid valid valid valid valid valid valid valid figure 45. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 46. external clock drive
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 61 v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00717 figure 47. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00718 figure 48. float waveform 4 8 12 16 20 24 28 32 36 60 50 40 30 20 10 frequency at xtal1 (mhz, 12-clock mode) i cc (ma) maximum idle su01631 typical i cc active 89c51ra2/rb2/rc2/rd2 maximum i cc active typical idle figure 49. i cc vs. freq valid only within frequency specifications of the device under test
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 62 v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00010 figure 50. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00011 figure 51. float waveform
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 63 v cc p0 ea rst xtal1 xtal2 v ss v cc v cc v cc i cc (nc) clock signal p89c51ra2xx P89C51RB2xx p89c51rc2xx p89c51rd2xx su01478 figure 52. i cc test condition, active mode, t amb = 25 c. all other pins are disconnected v cc p0 rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal ea su01479 p89c51ra2xx P89C51RB2xx p89c51rc2xx p89c51rd2xx figure 53. i cc test condition, idle mode, t amb = 25 c. all other pins are disconnected v cc 0.5 0.5v t chcl t clcl t clch t clcx t chcx su01297 figure 54. clock signal waveform for i cc tests in active and idle modes. t clcl = t chcl = 10 ns v cc p0 rst xtal1 xtal2 v ss v cc v cc i cc (nc) ea su01480 p89c51ra2xx P89C51RB2xx p89c51rc2xx p89c51rd2xx figure 55. i cc test condition, power down mode. all other pins are disconnected; v cc = 2 v to 5.5 v
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 64 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 65 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 66 lqfp44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 67 revision history date cpcn description 2002 july 18 9397 750 10129 modified ordering information table 2002 may 20 9397 750 09843 initial release
philips semiconductors preliminary data p89c51ra2/rb2/rc2/rd2xx 80c51 8-bit flash microcontroller family 8kb/16kb/32kb/64kb isp/iap flash with 512b/512b/512b/1kb ram 2002 jul 18 68 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2002 all rights reserved. printed in u.s.a. date of release: 07-02 document order number: 9397 750 10129

data sheet status [1] objective data preliminary data product data product status [2] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change notification (cpcn) procedure snw-sq-650a. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com.

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